1. Field
The following description relates to a technique for accurate computation when allocating instructions between a plurality of processing elements (PEs) performing computation iterations in parallel.
2. Description of the Related Art
In general, processing by hardware may not be able to properly handle a task because of the inherent inflexibility of hardware designs. This is especially true when a particular task is subject to modification. Unlike processing by hardware, processing by software processing can provide flexibility for and adaptability to various tasks. However, the speed of processing by software is generally inferior to that of hardware.
Reconfigurable architectures are computer architectures whose hardware structures can be reconfigured to be optimized for a particular task. In addition, reconfigurable architectures can provide benefits of both hardware processing and software processing. As a result, there has been growing interest in reconfigurable architectures, especially in the field of digital signal processing.
Digital signal processing generally involves multiple loop computations. In order to speed up loop computations, loop level parallelism (LLP), such as software pipelining, is widely used.
Software pipelining is based on the principal that even operations belonging to different iterations can be processed in parallel so long as the operations do not have any dependency from other operations. In particular, software pipelining offers better performance when it is applied to reconfigurable arrays. For example, operations that can be processed in parallel may be allocated between a plurality of processing units of a reconfigurable array for parallel processing.
In recent years, the demand has steadily grown for research into ways to effectively allocate instructions between a plurality of processing elements (PEs) as performed in pipelining, and even execute loop instructions having a memory dependency properly.